FPGA clock divider

FPGA crossover is believed to be a relatively frequent and relatively basic technology in FPGAs. The following is a specific explanation of the clock division of the FPGA.

Concept:

The FPGA clock is divided into the frequency of the system clock of the FPGA according to its own needs, so that it reaches the original 1/N times frequency. According to the value of N, it can usually be divided into even-numbered and odd-numbered.

Even frequency division:

Even frequency division, that is, N is an even number to divide the system clock. This design is mainly implemented by a counter. The design principle is as follows: the system reference clock is used as a trigger condition to make an up counter. When the counter value is (n/2 - 1), the output clock jumps. To implement a divide-by-4 program, do the following:

module div_4(clk,clr_n,clk_o);

input clk;

input clr_n;

Output clk_o;

reg [1:0] cnt_div;

reg clk_o_1;

always @ (posedge clk or negedge clr_n)

begin

if( !clr_n)

cnt_div <= 0;

else if(cnt_div == 2'b01)

cnt_div <= 0;< Br>

else

cnt_div <= cnt_div+1;

end

always @ (posedge clk or negedge clr_n)

begin< Br>

if(!clr_n)

clk_o_1<=0;

else if (cnt_div == 2'b01)

clk_o_1 <= ~clk_o_1;

end

assign clk_o=clk_o_1;

endmodule

odd frequency division:

odd multiple frequency division method when N is The system clock is divided at odd times. The principle is: set two identical counters with the maximum value of (n-1), one of which is triggered by the rising edge of the system clock, and the other is the triggering condition of the falling edge of the system clock; the output clock is at the counter value (n) -1)/2 and (n-1) respectively, flipping to obtain two clocks with a duty ratio other than 50%, and finally performing phase-OR operation on the two output clocks to obtain a duty ratio of 50%. Odd divided clock. The reference code to implement a divide-by-5 ​​clock is as follows:

module div_5(clk,clr_n,clk_o);

input clk;

Input clr_n;

output clk_o;

reg [2:0] cnt_div1;

reg [2:0] cnt_div2;

reg clk_o_1;< Br>

reg clk_o_2;

always @ (posedge clk or negedge clr_n)

begin

if( !clr_n)

cnt_div1 < = 0;

else if(cnt_div1 == 3'b100)

cnt_div1 <= 0;

else

cnt_div1 <= cnt_div1+ 1;

end

always@(posedge clk or negedge clr_n)

begin

if(!clr_n)

clk_o_1< =0;

else if (cnt_div 1== 3'b010)

clk_o_1 <= ~clk_o_1;

else if(cnt_div1 ==3'b100)< Br>

clk_o_1 <= ~clk_o_1;

end

always @ (negedge clk or negedge clr_n)

begin

if( ! Clr_n)

cnt_div2 <= 0;

else if(cnt_div2 == 3'b100)

cnt_div2 <= 0;

else < Br>

cnt_div2 <= cnt_div2+1;

end

always @ (posedge clk or negedge clr_n)

begin

if( !clr_n)

clk_o_2< =0;

else if (cnt_div2== 3'b010)

clk_o_2 <= ~clk_o_2;

else if(cnt_div2 ==3'b100)

clk_o_2 <= ~clk_o_2;

end

assign clk_o=clk_o_1