The difference between wire and reg in verilog HDL

wire means straight through, that is, the input changes, and the output is immediately reflected unconditionally (such as simple connection with NAND gate).

reg indicates that there must be a trigger, and the output will reflect the state of the input.

reg is equivalent to a storage unit, and wire is equivalent to a physical connection. Reg indicates that there must be a trigger. When there is no input, the original value can be maintained, but it is not directly related to the actual hardware circuit.

The difference between the two is that the register type data remains the last assignment, while the line type data needs to be driven continuously. Wire is used in continuous assignment statements, and reg is used in process assignment statements (initial, always). If the wire is connected without a drive, its value is z, and the default initial value of reg is the undefined value x.

In a continuous assignment statement, the result of the calculation on the right side of the expression immediately updates the left side of the expression. In understanding, equivalent to a logic directly connected to a line, this logic corresponds to the right side of the expression, and this line corresponds to wire. In a process assignment statement, the result of the calculation on the right side of the expression is placed in a variable under the trigger of a condition, and this variable can be declared as a reg type. Depending on the trigger condition, the process assignment statement can model different hardware structures: if the condition is a rising or falling edge of the clock, then the hardware model is a trigger; if the condition is a high level of a signal or Low level, then this hardware model is a latch; if this condition is a change in any operand to the right of the assignment statement, then the hardware model is a combinational logic.

For combinational logic output variables, you can use assign directly. That is, if it is not specified as the reg type, then the default is a 1-bit wire type, so there is no need to specify a 1-bit wire type variable. Of course, the wire type is specified specifically, which may be multiple bits or to make the program easy to read. Wire can only be assigned consecutively by assign, reg can only be assigned in initial and always.

The input port can be driven by wire/reg, but the input port can only be wire; the output port can be wire/reg type, the output port can only drive wire; if the output port is assigned in the process block, it is reg Type, if assigned outside the process block, it is net type (wire/tri). Declaring a bidirectional port with the keyword inout, the inout port cannot be declared as a reg type, only the wire type.

The default signal is the wire type, and the reg type is declared. The default here refers to the output signal is declared as output when it is wire. If it is a module internal signal, it must be declared as wire or reg.

For the always statement, the assignment should be declared as reg, and wire should be used when assigning assign continuously.

When the module is called The signal type determination method is summarized as follows:

? The signal can be divided into a port signal and an internal signal. The signals that appear in the port list are port signals, and the other signals are internal signals.

? For port signals, the input port can only be of type net. The output port can be either a net type or a register type. The register type is used if the output port is assigned a value in the process block; if it is assigned outside the process block (including the instantiation statement), it is the net type.

? The internal signal type is the same as the output port and can be of type net or register. The judgment method is also the same as the output port. If the value is assigned in the process block, it is the register type; if it is assigned outside the process block, it is the net type.

? If the signal needs to be assigned both in the process block and outside the process block. This situation is possible, such as a decision signal. An intermediate signal conversion is required at this time.

The following are common errors and corresponding error messages

? Use a procedure statement to give a signal of type net or forgotten to declare type Assignment.

Information: illegal …… assignment.

?Connect the output of the instance to a signal declared as a register type.

Information: <name> has illegal output port specification.

?Declare the module's input signal as register type.

Information: incompatible declaration, <signal name> ……