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Status and Control Register

The status and control registers are composed of the flag register EFLAGS, the instruction pointer EIP, and four control registers, as shown in Figure 2.1:
Flag Register
Instruction Pointer
Machine Status Word
Intel Reserved
page fault address
page directory address

EFLAGS
EIP
CR0
CR1
CR2
CR3

FIG state 2.1 And control register
1. Instruction pointer register and flag register
instruction pointer register EIP stores the offset (offset) of the next instruction to be executed. This offset is relative to the currently running code segment register. For CS. The offset plus the base address of the current code segment forms the address of the next instruction. The lower 16 bits of the EIP can be accessed separately, calling it the instruction pointer IP register for 16-bit addressing.
The flag register EFLAGS stores the control flags for the processor, as shown in Figure 2.2. The 1st, 3rd, 5th, 15th, and 18th to 31st bits in the flag register are not defined.

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