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Explanation of various keywords in Verilog HDL language

  
 1, module_endmodule

Structure Description Statement

2, initial Initialize variables at the beginning of the simulation, The excitation waveform can be generated as a test simulation signal for the circuit
3, always Repeatedly executed, format: always <timing control> <statement> Br>4, task_endtask
5, function_endfunction

Function definition

6, always block (1) Both combinational logic and sequential logic can be described;
(2) Internal statements are executed sequentially, and inter-block statements are executed in parallel.
7,sign Describe combinatorial logic
8, use instance components

Block statement

9, begin_end order block
10, fork_join < Wbr> parallel block

conditional statement

11, if_else
12, case_endcase

loop statement

13, foever
14, for
15, repeat
16, while

data type (19 4 of them)

17, reg
18, wire
19, integer
20, parameter

Edge Signals

21, posedge
22, negedge

Assignment Statement

23, Non_Blocking (1) The assignment can be completed after the end of the block;
< Wbr> (2) For writing synthesizable sequential logic module.
24, Blocking (1) After the assignment statement is executed, the block ends;
< Wbr> (2) There are unpredictable results for the design of sequential circuits. (described later)



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